# Design of 4-Bit Cpu Essay

Designing a 4-bit Computer| For submission to Mr. Manoj Ghimire| | | | Kishor Adhikari(063bex416) Priya Agrawal(063bex425) Sanuj Shakya(063bex433)| 5/11/2010| | Contents Introduction2 Initial Block Diagram2 Instructions to be Implemented3 Decoder section4 Timing Section5 Bus Control5 4 bit ALU AND COMPLEMENTER6 Executions6 Control Logic10 Introduction A computer design is the hardware design procedure of a computer on the basis of the specifications required i. e. the instructions to be supported by the computer.

It includes the determination of what hardware should be used and how the parts must be interconnected for the computer to operate as intended. This report contains a brief discussion on the design procedure of a very basic computer organization. The design has been completed as an assignment for the course Computer Architecture and Design and has been submitted to our lecturer Manoj Ghimire. The design procedure is as follows. Initial Block Diagram Let us consider a block diagram for a 4 bit computer as shown below.

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Subtract Immediate data from : SUI A, SUI B, SUI C, SUI D 26. Subtract with borrow Immediate data from : SBI A, SBI B, SBI C, SBI D 27. Increase : INC A, INC B, INC C, INC D 28. Decrease : DCR A, DCR B, DCR C, DCR D 29. Complement : CMP A, CMP B, CMP C, CMP D 30. Out : OUT A, OUT B, OUT C, OUT D 31. No operation : NOP Decoder section Since we have a total of 30 different types of operations, we require a minimum of 5 bits (25 = 32) for representing all of them. Also we require additional 2 bits for representing the instructions in each operation as we have a maximum of four different instructions in each operation type.

Thus an instruction code will be a 7 bits word; the most significant 5 bits representing the type of operation and the two least significant bits determining the exact operand for that operation. For this requirement, we design the instruction decoder as follows. Its connections to the control logic are also shown. Control Signals 5 4 3 2 0 1 Instruction Register (7 bits) 5*32 DECODER 2*4 DECODER Control Logic D0 D31 T0 T3 D D35 C B D1 D32 A D30 6 Fig. 2: Decoder Circuitry with connection to Control Logic In fig, the decoded signals D0 – D28 represent the corresponding operation from No. – 29 of the above listed operations and the signals D29 – D31 represent NOP. The signals D32 – D35 references one of the 4 registers as indicated above. Timing Section Sequence Counter 2*4 Decoder Control Logic Control Signals T0 T1 T2 T3 D0 D35 CLK CLR CNT Fig: Timing Circuitry with connection to Control Logic The sequence counter is a 2 bit binary counter which counts from 00 to 11 at every clock pulse when CNT signal is HIGH. When CLR is HIGH, the count is cleared to 00. The output of SC is decoded to give four timing signals T0, T1, T2 and T3. The CNT signal becomes HIGH when the “START” signal is applied at the input.

When the execution is completed CNT signal is cleared to LOW and CLR signal is set to HIGH for the next instruction to be executed. For the execution of each instruction, the instruction code in the IR has to be decoded first. Thus the decoding will be performed at the first time cycle T0 i. e. : T0: D0 – D31 Bus Control S2S1S0| Register Select| 000| A| 001| B| 010| C| 011| D| 100| INPR| 101| Y| 110| -| 111| -| BUS Control S0 S1 S2 4 bit BUS 4 bit ALU AND COMPLEMENTER F/A MUX AS0 AS1 B0 B0 0 1 A0 C D0 F/A MUX B1 B1 0 1 A1 D1 F/A MUX B3 B3 0 1 A3 D3 C0 C1 COUT AS0 AS1 AS0 AS1 COMPLEMENTER A3

A2 A1 A0 A3 A2 A1 A0 CMP Fig: A 4 bit ALU circuitry AS2AS1AS0| MUX O/P (Y)| OUTPUT(D)| DESCRIPTION| 000| B| A+B| Add| 001| B| A+B+1| Add with carry| 010| B’| A+B’| Subtract with borrow| 011| B’| A+B’+1| Subtract| 100| 0| A| Transfer| 101| 0| A+1| Increment| 110| 1| A-1| Decrement| 111| 1| A| Transfer| For the last case ,If CMP = 1 A’ Complement Executions The executions of the instruction begin from timing cycle T1, after being decoded at T0. 1. 2. Load (D0 = 1) T1: A/B/C/D <> a. D0T1: S2S1S0 <> b. D0D32T1: ALD <> D0D33T1: BLD <> D0D34T1: CLD <> D0D35T1: DLD <> c. D0T1:SC <> 3.

Move to A (D1 = 1) T1: A <> d. D1D33T1: S2S1S0 <> D1D34T1: S2S1S0 <> D1D35T1: S2S1S0 <> e. D1T1: ALD <> 4. Move to B (D2 = 1) T1: B <> f. D2D32T1: S2S1S0 <> D2D34T1: S2S1S0 <> D2D35T1: S2S1S0 <> g. D2T1: BLD <> 5. Move to C (D3 = 1) T1: C <> h. D3D32T1: S2S1S0 <> D3D33T1: S2S1S0 <> D3D35T1: S2S1S0 <> i. D3T1: CLD <> 6. Move to D (D4 = 1) T1: C <> j. D4D32T1: S2S1S0 <> D4D33T1: S2S1S0 <> D4D34T1: S2S1S0 <> k. D4T1: DLD <> 7. Add to A (D5 = 1) T1: X <> T2: Y <> T3: A <> l. D5D33T1: S2S1S0 <> D5D34T1: S2S1S0 <> D5D35T1: S2S1S0 <> m. D5T1: XLD <> n. D5T2:S2S1S0 <> AS1AS0C <> YLD <> o. D5T3:S2S1S0 <>

ALD<> 8. Add to B (D6 = 1) T1: X <> T2: Y <> T3: B <> p. D6D32T1: S2S1S0 <> D6D34T1: S2S1S0 <> D6D35T1: S2S1S0 <> q. D6T1: XLD <> r. D6T2:S2S1S0 <> AS1AS0C <> YLD <> s. D6T3:S2S1S0 <> BLD <> 9. Add to C (D7 = 1) T1: X <> T2: Y <> T3: A <> t. D7D32T1: S2S1S0 <> D7D33T1: S2S1S0 <> D7D35T1: S2S1S0 <> u. D7T1: XLD <> v. D7T2:S2S1S0 <> AS1AS0C <> YLD <> w. D7T3:S2S1S0 <> CLD <> 10. Add to D (D8 = 1) T1: X <> T2: Y <> T3: A <> x. D8D32T1: S2S1S0 <> D8D33T1: S2S1S0 <> D8D34T1: S2S1S0 <> y. D8T1: XLD <> z. D8T2:S2S1S0 <> AS1AS0C <> YLD <> {. D8T3:S2S1S0 <> DLD <> 11. Add to A with carry (D9 = 1) 12.

Add to B with carry (D10 = 1) 13. Add to C with carry (D11 = 1) 14. Add to D with carry (D12 = 1) Same micro-operations as ADD except for the ALU signal AS1AS0C 15. Subtract from A (D13 = 1) 16. Subtract from B (D14 = 1) 17. Subtract from C (D15 = 1) 18. Subtract from D (D16 = 1) Same micro-operations as ADD except for the ALU signal AS1AS0C <> 19. Sub from A with borrow (D17 = 1) 20. Sub from B with borrow (D18= 1) 21. Sub from C with borrow (D19 = 1) 22. Sub from D with borrow (D20 = 1) Same micro-operations as ADD except for the ALU signal AS1AS0C <> 23. Add immediate data (D21 = 1) T1: X <>

T2: Y <> T3: A/B/C/D <> |. D21T1: S2S1S0 <> }. D21T1: XLD <> ~. D21D32T2:S2S1S0 <> D21D33T2:S2S1S0 <> D21D34T2:S2S1S0 <> D21D35T2:S2S1S0 <> . D21T2:AS1AS0C <> D21T2: YLD <> ?. D21T3:S2S1S0 <> ?. D21D32T3: ALD <> D21D33T3: BLD <> D21D34T3: CLD <> D21D35T3: DLD D21 T3S:SC<> 24. Add immediate data with carry(D22 = 1) T1: X <> T2: Y <> T3: A/B/C/D <> ?. D22T1: S2S1S0 <> ?. D22T1: XLD <> ?. D22D32T2:S2S1S0 <> D22D33T2:S2S1S0 <> D22D34T2:S2S1S0 <> D22D35T2:S2S1S0 <> ?. D22T2:AS1AS0C <> ?. D22T2: YLD <> ?. D22T3:S2S1S0 <> ?. D22D32T3: ALD <> D22D33T3: BLD <> D22D34T3: CLD <> D22D35T3: DLD <> ?.

D22T3: SC <> 25. Subtract immediate data (D23 = 1) T1: X <> T2: Y <> T3: A/B/C/D <> ?. D23T1: S2S1S0 <> ?. D23T1: XLD <> ?. D23D32T2:S2S1S0 <> D23D33T2:S2S1S0 <> D23D34T2:S2S1S0 <> D23D35T2:S2S1S0 <> ?. D23T2:AS1AS0C <> ?. D23T2: YLD <> ?. D23T3:S2S1S0 <> ?. D23D32T3: ALD <> D23D33T3: BLD <> D23D34T3: CLD <> D23D35T3: DLD <> ?. D23T3: SC <> 26. Subtract immediate data with borrow(D24 = 1) T1: X <> T2: Y <> T3: A/B/C/D <> ?. D24T1: S2S1S0 <> ?. D24T1: XLD <> ?. D24D32T2:S2S1S0 <> D24D33T2:S2S1S0 <> D24D34T2:S2S1S0 <> D24D35T2:S2S1S0 <> ?. D24T2:AS1AS0C <> ?. D24T2: YLD <> ?. D24T3:S2S1S0 <> ?.

D24D32T3: ALD <> D24D33T3: BLD <> D24D34T3: CLD <> D24D35T3: DLD <> ?. D24T3: SC <> 27. Increase A/B/C/D (D25 = 1) T1: Y <> T2: A/B/C/D <> ?. D25D32T1: S2S1S0 <> D25D33T1: S2S1S0 <> D25D34T1: S2S1S0 <> D25D35T1: S2S1S0 <> ?. D25T1: AS1AS0C <> ?. D25T1: YLD <> ?. D25T2: S2S1S0 <> ?. D25D32T2: ALD <> D25D33T2: BLD <> D25D34T2: CLD <> D25D35T2: DLD <> ?. D25T2: SC <> 28. Decrease A/B/C/D (D26 = 1) T1: Y <> T2: A/B/C/D <> ?. D26D32T1: S2S1S0 <> D26D33T1: S2S1S0 <> D26D34T1: S2S1S0 <> D26D35T1: S2S1S0 <> ?. D26T1: AS1AS0C <> ?. D26T1: YLD <> ?. D26T2: S2S1S0 <> ?. D26D32T2: ALD <> D26D33T2: BLD <>

D26D34T2: CLD <> D26D35T2: DLD <> ?. D26T2: SC <> 29. Complement A/B/C/D (D27 = 1) T1: Y <> T2: A/B/C/D <> ?. D27D32T1: S2S1S0 <> D27D33T1: S2S1S0 <> D27D34T1: S2S1S0 <> D27D35T1: S2S1S0 <> ?. D27T1: AS1AS0C <> CMP <> ?. D27T1: YLD <> ?. D27T2: S2S1S0 <> ?. D27D32T2: ALD <> D27D33T2: BLD <> D27D34T2: CLD <> D27D35T2: DLD <> ?. D27T2: SC <> 30. Out A/B/C/D (D28 = 1) T1: OUTR <> ?. D28D32T1: S2S1S0 <> D28D33T1: S2S1S0 <> D28D34T1: S2S1S0 <> D28D35T1: S2S1S0 <> ?. D28T1: OUTRLD <> ?. D28T1: SC <> 31. NOP (D29 = 1) 32. NOP (D30 = 1) 33. NOP (D31 = 1) T1: SC <> D29T1: SC <> D30T1: SC <>

D31T1: SC <> Control Logic Control Logic T0 T3 D0 D35 ALD BLD CLD DLD OUTRLD S0 S1 S2 XLD YLD AS1 AS0 C SC CMP The control signals are the output signals obtained from above control logic block. Each control signal can be obtained as the logical combination of the input bits depending upon the above executions i. e. the logic gates associated with the particular control signal is derived by scanning the above listed micro-operations to find the statements that specify the particular operation. For e. g. the control signal ALD is obtained by OR-ing all the statements that specify ALD

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