DIGITAL DESIGN FLOW OPTIONS A Thesis Presented in Partial Fulfillment of the Requirements for the Degree Master of Science in the Graduate School of The Ohio State University By Sagar Vidya Reddy, B. E. ***** The Ohio State University 2001 Master’s Examination Committee: Professor. Joanne E. DeGroat, Adviser Professor. Steven B. Bibyk Approved by Adviser Department of Electrical Engineering ABSTRACT VLSI (Very Large Scale Integration) IC design flow is a term used to describe the process of chip design.
The circuit designer/design group uses a multitude of computer aided design tools throughout the design flow to tape out an integrated circuit IC. There are numerous computer aided design (CAD) tools available commercially to help such designers in design. The design tools and the order in which they are used is termed as the design flow. CAD tools however do have certain problems associated with them. Cost, accessibility, compatibility and reliability are a few of such problems.
At the university level, usability, tutorials and adequate documentation is needed to facilitate students to adapt and familiarize themselves with the CAD tool suites in a short time. In mixed signal chips, there are two distinct phases of design, the analog and the digital part. The analog part of the chip (probably containing a few hundred ii transistors) consumes a considerable amount of time to design. The digital part of the chip (probably containing tens of thousands to a million transistors) needs to be developed in a relatively short period of time. Thus design team needs to place a few thousand gates quickly and reliably.
To support this, the choice of CAD tools becomes critical. A good CAD tool can drastically reduce the time required to design a large digital block. The scope of this thesis is to search for an optimal digital design flow. The aim is to use a set of commercial and open sourced tools and bring digital logic design to such a stage that the design can be shipped for fabrication or attached to an analog entity for fabricated into a mixed signal chip. The stress in this thesis is going to be on evolving a streamlined design flow, which is quick, cheap, reliable and acceptable.
Conclusions will be reached as to how a particular tool is best suited for each stage of design. These design suites will be compared and contrasted with respect to various qualities like cost, accessibility, usability, etc. Most non-commercial CAD tools fail to meet the industry’s requirements when the design becomes technology specific. Most industrially accepted CAD tools are expensive. It is here that a cheaper design alternative is required. Solutions to this problem using Electric and TestBencher are suggested in this thesis. In this document, the primary focus is on three tools, TestBencher, X -HDL3 and Electric.
These CAD tools were chosen, as they seemed ideal for a university environment. iii All the chapters start with a brief explanation of a design stage. After a brief explanation, every chapter is further subdivided into various sections. Each section deals with a particular aspect of design and how the design can be completed using one of the CAD tools. Throughout this document an example based approach is adopted. The examples chosen are simple circuits to increase readability. iv To Nipa v ACKNOWLEDGMENTS I would like to thank my friend Nipa for her continuous motivation, moral support, encouragement and love. I would like to thank Prof.
DeGroat for her suggestions, support, guidance and the inspiration I got while working with her during the course of my masters degree. I am especially indebted to Prof. Bibyk for all his invaluable suggestions, advice, support, guidance and help. vi VITA Dec 24, 1977 Born – Guntur, India. 1995 – 1999 B. E. Electrical & Electronics Engineering, Bangalore University, Bangalore, India. 1999- present Masters student, The Ohio State University FIELDS OF STUDY Major Field: Electrical Engineering vii TABLE OF CONTENTS Page Abstract………………………………………………………….. … Dedication…………………………………………………………… Acknowledgments…………………………………………………..
Vita…………………………………………………………………… List of Figures………………………………………………………… List of Tables…………………………………………………………. Chapters 1. Introduction………………………………………………… 1. 1 Generic IC design Flow……………………………. 1. 2 Problem description……………………………….. 1. 3 Ideal solution………………………………………. 1. 4 Proposed solution………………………………….. 1. 5 Research objective…………………………………. 2. Design idea …………………………………………………. 2. 1 Evolving a design Idea……………………………… viii 1 1 7 8 9 10 12 14 ii v vi vii xii xvii 2. 2 Capturing a design Idea……………………………… 2. 3 Abstract design idea simulation……………………… 2. 4 Simulation of theory of operation using C…………… 2. 5 HDL for simulation…………………………………… 2. Introduction to TestBencher…………………………… 3. Behavioral description………………………………………… 3. 1 Behavioral description to RTL………………………… 3. 2 Introduction to X-HDL3……………………………… 3. 3 TestBencher for behavioral description……………… 3. 4 Test bench generation in WaveFormer Pro…………… 3. 5 Verilog to VHDL conversion and vice versa………… 4. Structural description…………………………………………. 4. 1 Simulation and timing analysis………………………. 4. 2 Hierarchy……………………………………………… 4. 3 Analog simulation of structural description…………… 4. 4 Structural description to FPGA………………………… 4. 5 Structural description to ASIC using Renoir (Mentor Graphics) ………………………. 4 17 17 21 25 26 28 29 38 38 41 43 44 47 49 53 63 65 66 69 70 5. IC layout, DRC and LVS ………………………………………… 5. 1 Cadence versus other tools………………………………. 5. 2 Why Cadence at the last step? ……………………………. 5. 3 Starting a layout for MOSIS……………………………… ix 5. 4 Selecting a process technology……………………………. 5. 5 SCMOS versus specific vendor technology………………. 5. 6 Layout formats……………………………………………. 5. 7 Setting up Cad tools…………………………. …………… 5. 8 Submitting to MOSIS……………………………………… 5. 9 Layout using Electric………………….. …………………… 5. 10 Loading vendor technologies in Electric…………………… 5. 11 Layer mapping in Electric…………………………………… 5. 2 Standard cell layout in Electric…………………………… 5. 13 Manual layout generation in Electric………………………. 5. 14 Manual placement and semi-automatic routing options …… 72 73 76 77 79 80 81 83 85 86 87 91 97 100 5. 15 VHDL synthesis: Silicon Compiler in Electric……………… 5. 16 Simulation…………………………………………………… 5. 17 Mixed signal design and exporting to Cadence……………… 5. 18 DRC…………………………………………………………. 104 5. 19 LVS…………………………………………………………. 106 5. 20 Pad frame…………………………………………………….. 107 5. 21 Other interesting features of Electric………………………… 6. Summary and Conclusion……………………………………………… 111 117 6. 1 Summary……………………………………………………… 117 6. Conclusion…………………………………………………….. 122 Appendix A. Behavioral description of SAR……………………………… x 124 Appendix B. Structural description of SAR……………………………… Bibliography……………………………………………………………… 132 149 xi LIST OF FIGURES Figure 1. 1 Generic design flow………………………………………….. 2. 1 Current status design idea…………………………………… 2. 2 Black box block diagram…………………………………….. 2. 3 Functional block diagram……………………………………. 2. 4 Flow chart of SAR…………………………………………… 2. 5 Simulation result 1 for 0v input……………………………… 2. 6 Simulation result 2 showing the expected result with 1 bit error…. …………………………………….. Page 2 13 15 15 16 19 20 2. 7 Simulation result 3. …………………………………………. 20 2. 8 TestBencher overview…………………………………………. 24 2. 9 D[7:0] shows the result for input voltage of 44………………. 3. 1 Current status, behavioral description………………………… 3. 2 X-HDL3 interface for behavioral to RTL. …………………… 3. 3 Pre/ post process interface of X-HDL3……………………… 3. 4 Illustration of instantaneous test bench creation……………… 3. 5 X-HDL3 interface for Verilog ? VHDL conversion………… xii 25 27 30 35 40 41 4. 1 Current status structural description………………………… 4. 2 Simulation of structural Dff………………………………… 4. 3 User defined setup and hold times…………………………. 4. 4 Hierarchy of the SAR circuit……………………………….. . 5 Hierarchy in TestBencher…………………………………… 4. 6 Screen capture of Microwind showing direct verilog file input……………. ………………………. 4. 7 Microwind simulation 1…………………………………….. 4. 8 Microwind simulation 2…………………………………….. 4. 9 FPGA Synthesis Design flow Using MyCad………………… 53 4. 10 MyCad’s FPGA synthesizer………………………………… 44 46 46 48 48 50 51 52 61 4. 11 One bit adder FPGA………………………………………… 62 4. 12 8 Bit adder FPGA…………………………………………… 4. 13 Renoir ASIC design Flow. ………………………………… 5. 1 Current status layout, DRC, LVS…………………………… 5. 2 Dflipflop synthesized by Microwind………………………… 5. 3 DRC failure of Microwind’s Dff in Cadence………………… 5. Design flow for layout generation…………………………… 5. 5 MOSIS recommended design flow…………………………… 5. 6 AMI 0. 8 technology 2 x 2 AND OR gate …………………… 5. 7 AMI 0. 8 technology 2×2 AND OR gate GDS II plot………… 76 5. 8 Electric interface……………………………………………… xiii 78 63 64 66 68 68 70 72 75 5. 9 Electric interface for importing LEF files…………………….. 82 5. 10 All cells of SCMOS_SUBM at lambda=0. 30 (AMI 0. 80)….. 83 5. 11 Flexible layer mapping interface in Electric…………… 5. 12 Standard cell formation in Electric……………………… 5. 13 Manual layout generation in Electric…………………… 5. 14 Designer’s floor plan…………………………………….. 5. 5 Standard cells connected with generic arcs……………… 5. 16 Standard cells after maze routing……………………….. 5. 17 River routing of buses…………………………………… 5. 18 Result of river routing…………………………………… 5. 19 VHDL interface in Electric……………………………… 5. 20 Place and route options………………………………….. 5. 21 Layout generated automatically………………………….. 5. 22 Standard cells used. Lines indicate the routed wires……… 5. 23 Inverter layout under simulation…………………………… 5. 24 SPICE simulation………………………………………….. 5. 25 ALS simulation…………………………………………….. 5. 26 Inverter design imported into Cadence…………………….. 5. 27 8 bit comparator imported into Cadence Virtuoso…………. . 28 DRC failure due to mismatching Libraries………………… 5. 29 DRC customization window………………………………… 5. 30 Automatic Schematic extraction in Electric………………. xiv 84 85 86 87 88 89 89 90 93 94 95 96 97 98 99 102 103 104 106 107 5. 31 Different Pads available in MOSIS TSMC 0. 25………… 5. 32 8 Bit comparator core in Pad Frame……………………… 5. 33 Zoomed in View of a PAD……………………………… 5. 34 The complete chip………………………………………. 5. 35 3-D view of a Dflipflop…………………………………. 5. 36 3-Dview of a Dflipflop………………………………….. 5. 37 Wasteful layout of an inverter…………………………… 5. 38 Layout after compaction………………………………… 5. 39 Compaction Results……………………………………… 5. 0 PLA generated for equations in table 5. 11……………….. 6. 1 Recommended design flow for quick digital design……….. 6. 2 Budget oriented design flow……………………………….. Appendix A A1 D[7:0] shows the result for input voltage of 44……………. A2 Result with bus d[7:0] expanded …………………………… A3 Result showing the expected 1bit error……………………… A4 Result with bus d[7:0] expanded……………………………. Appendix B B1 Simulation result of dff ……………………………………… B2 Simulation result of clock divider …………………………… B3 Simulation result of clock divider with bus expanded ………. B4 Simulation result of logic block 1…………………………….. xv 108 109 110 110 111 112 113 113 115 116 119 120 28 129 130 131 133 135 136 138 B5 Simulation result with bus d[31:0] expanded………………… B6 Simulation result of main register……………………… 139 ……. 141 143 144 146 147 148 B7 Simulation of digital part of SAR. …………………………… B8 Simulation of digital part of SAR. …………………………… B9 Simulation result of MYCHIP………………………………… B10 Simulation result 2 of MYCHIP……………………………… B11 Simulation result 3 of MYCHIP……………………………… xvi LIST OF TABLES Table Page 1. 1 Properties of an ideal tool kit…………. ……………….. 1. 2 Aim of thesis…………………………………… …….. 2. 1 SAR specs sheet……………………………………….. 2. 2 C code for design idea simulation……………………… 2. Verilog Code for design idea simulation………………. 3. 1 Behavioral description of dff…………………………… 3. 1 RTL code generated X-HDL3………………………….. 3. 3 Code not translatable by X-HDL3……………………… 3. 4 Erroneous code generated by x_HDL3…………………. 3. 5 Error replaced by Perl script……………………………. 3. 6 Structural description of Dff……………………………. 4. 1 Structural description of Dff……………………………. 4. 2 8 bit adder structural description……………………….. 5. 1 Resources provided by MOSIS for designers…………… 5. 2 Features to be provided by vendors for their libraries……….. xvii 6 8 12 15 19 24 26 27 28 31 33 33 47 61 63 5. 3 Verification before starting a layout…………………………. . 4 Electric salient features………………………………………. 5. 5 Semiautomatic routing options in Electric…………………… 5. 6 Problems associated with semiautomatic routing…………….. 5. 7 Flat VHDL code for Silicon Compiler………………………… 5. 8 Silicon Compiler options…………………………………….. 5. 9 List of simulation export formats in Electric………………… 5. 10 DRC options………………………………………………… 5. 11 PLA generation equations…………………………………… 6. 1 Salient features of TestBencher, X-HDL3, Electric………….. 6. 2 CAD tools encountered……………………………………………………. A1 Behavioral description of SAR in Verilog……………………. A2 VHDL file generated by X-HDL3…………………………….
B1 Verilog description of dff …………………………………….. B2 Verilog description of clock divider…………………………… B3 Verilog description of logic block 1…………………………… B4 Verilog description of main register…………………………… B5 Verilog description of digital part of SAR. …………………… B6 Simulation of digital part of SAR……………………………… B7 Simulation of digital part of SAR. ……………………………. B8 Simulation result of MYCHIP………………………………… 68 69 75 78 80 84 88 93 103 105 121 124 125 132 134 137 140 142 143 144 145 xviii xix CHAPTER 1 INTRODUCTION There are several hundred CAD tool suites in the market today, which can help us in integrated circuit (IC) design.
Based on the requirements, a design team needs to appropriately choose the right set of CAD tools for development. This document is aimed at helping university based design teams in establishing a quick and a reliable design flow. The primary CAD tool suites used are TestBencher, XHDL3 and Electric. Section 1. 1 reviews a generic IC design flow. 1. 1 GENERIC IC DESIGN FLOW Design Flow is a term used to describe the various design phases of an IC design. The first thing needed to start a design, is a specification of what needs to 1 be done (‘specs’). Given a specification, the most general approach adopted is shown in figure 1. 1.
Figure 1. 1: Generic IC design flow Design idea: Based on the specification given, the design team forms a general idea about the solution to the problem. System level decisions are made regarding the design and a general consensus is reached regarding the major functional blocks 2 that that go into the making of the chip. At the end of this stage, a general block diagram solution of the design is agreed upon. CAD tools are generally not needed at this stage. Behavioral description Hardware Description Languages (HDLs) are used to model the design idea (block diagram). Circuit details and electrical components are not specified.
Instead, the behavior of each block at the highest level of abstraction is modeled. Simulations are then run to see if the blocks do indeed function as expected and the whole system performs as a whole. Behavioral descriptions are important as they corroborate the integrity of the design idea. Structural description HDLs are used to describe the construction of the design at the next level of abstraction. In this stage, various electronic components and circuit details that go into the making of the various blocks of the system are modeled. These may include primitives like logic gates and very large pre-designed blocks called standard cells.
Simulations are then run on each block separately to test its operation. Once this is completed, all blocks are interconnected and a system level 3 simulation is run. A successful simulation ensures that an electronic circuit can indeed be built to match the behavioral description. Schematic description A schematic description is similar to a structural description. In a rigorous context, schematics can be considered to be at a lower level of abstraction, as the topology of the circuits needs to be considered. In most cases, graphical tools are used to build the circuits in a virtual breadboard like environment.
Just as in the previous stage, various electronic components like logic gates and standard cells are placed and interconnected to make the circuit blocks. This is an alternative form of structural description with more attention being paid to topology. A successful simulation ensures that an electronic circuit that matches the behavioral description can be built. Layout description This is the lowest level of abstraction possible in circuit description. In this stage, the circuit is described with respect to the silicon and other materials that go into the making of the IC. Extreme attention is paid to geometry of the components. In other words, this is how the IC would look, if we took a closer look at it through the microscope. Parasitic elements need to be extracted at each stage. The placement and interconnects of each and every individual entity of the previous stage need to be specified. Extensive simulations of each block are run in this stage. A floor plan of the chip is made and the blocks are routed together. After the routing phase, simulations of the entire design are run. LVS After the completion of the layout description of each block, a Layout vs. Schematic (LVS) check is performed. This ensures that the layout is in onformance with the schematic. The design process moves back and forth between Layout, LVS and DRC. DRC This stage is often dependent on the final process technology that is used to manufacture the chip. The design rule check ensures that the rules laid down by the fabrication process technology are not violated. A good example would be, some 5 processes need transistors, wires and polysilicon to be of a certain minimum width. The layout would have to be drawn based on such constraints. The design toggles between Layout, LVS and DRC. CIF, GDS II This is the final stage before fabrication.
Most fabrication plants accept submissions in CIF or GDS II format (refer to chapter5). These are computergenerated files that describe the IC layout. They incorporate all the necessary details for manufacturing the chip. MOSIS (section 5. 3) accepts submissions in both CIF and GDS II formats and these files can be submitted electronically. A chip design team’s job comes to a momentary pause until the first few prototyped chips arrive from the fabrication plant. After the ‘silicon’ arrives, the testing phase begins. The first basic tests include a functional verification of the chip under ideal conditions.
Once the functionality is verified, extensive tests are performed by stretching various electrical parameters like frequency of operation and temperature to extremities. The chip’s behavior is then documented into the chip’s user manual. 6 1. 2 PROBLEM DESCRIPTION Every stage of the design flow (section 1. 1) involves a CAD tool. Thus, the choice of the CAD tools dictates the ease and expediency of the design process. Every tool has some salient features that make it advantageous for a certain design phase. CAD tools should facilitate chip design in as short a period of time as possible.
At the same time the design needs to be reliable and robust. Depending on the choice of the tool, and by taking advantage of its salient features, an optimal solution to traverse through the digital flow can be reached. Table 1. 1 enumerates the essential properties that CAD tool suites and need to posses. Properties of CAD tool suites. 1. Cost Effective. 2. Accessible. 3. Conform to industry standards. 4. Acceptable by the industry. 5. Accurate. 6. Scalable to the latest technology. 7. Adequate support and documentation. 8. Platform independent. 9. Networking capability. 10. User-friendly. 1. Interface with other tools. Table 1. 1: Essential properties of a CAD tool suites. 7 The problem at hand can now be summed up as: What collection of tools, possessing as many as the above-mentioned properties, would help us evolve a better design flow? 1. 3 IDEAL SOLUTION. An ideal solution to the above problem would be to use one tool from a single vendor, which possesses all of the above properties (table 1. 1). Unfortunately such a tool is not available. The reason being that every tool has some unique quality, which makes it more useful than others in some aspect of the design flow.
It is thus left to the discretion of the design team to choose the tools that best fit their needs and budget. In some cases, especially in big companies like HP, IBM, SGI, Intel, the design flow is so customized, that they develop ‘in-house’ CAD tool suites to suit their needs. In this document, however, the thrust is going to be from the point of view of a generic budget oriented university based design team. Apart from the properties mentioned in table 1. 1, an ideal solution for such a team would include a collection of tools that are cheaper than most commercial tools and are easily accessible with good documentation.
It would be even better if the software were Open Sourced. 8 1. 4 PROPOSED SOLUTION It is not possible to explore all of the available tools. Thus, a few of the tools that fall within the reach of a university based design team are explored. Most universities already have an established design flow with tools from vendors like Mentor Graphics and Cadence. However, in this document, various other tools that are relatively easier to work with, cheaper to obtain, and accepted by the industry are explored. The aim of this document is summarized in table 1. 2. After careful scrutiny of some of the well-known CAD tool suites (table 6. ), TestBencher, XHDL and Electric were chosen for implementing a complete design flow. The Proposed Solution is to use TestBencher for Verilog descriptions, X-HDL3 for verilog to VHDL conversion and Electric for schematic and Layout descriptions. An example-based approach is used in this document to illustrate every stage of the design. The SAR circuit is used as an example circuit to show the working of TestBencher and an 8-bit comparator circuit is used for Electric. Aim of this thesis 1. Establish a design flow for an efficient tape out of chips. 2. Provide a digital flow for mixed signal design. 3.
Establish a cost effective design flow. 4. Establish a time saving design flow. 5. Gain depth into the usefulness of synthesis, place and route tools. 6. Establish a design flow on platforms like Windows and Linux. 7. Serve as a guide/ tutorial for students in digital VLSI design. Table 1. 2: aim of thesis 9 This document contains 6 chapters. The chapters are a walkthrough of the design flow with illustrations of the usage of TestBencher and Electric at every stage. Deviations into an ASIC and an FPGA are briefly discussed in chapters 3 and 4. 1. 5 Research objective Before delving into the design process, a few things need to be kept in ind. Building a chip alone does not solve the entire problem. For example, consider the SAR type A/D. A chip can be taped out using the design flow suggested in this document. However, a successful chip tape out is just a part of the solution. The entire solution should include a complete interface, to say, a computer or a DSP board. Thus, a PCB needs to be designed as well. In big corporations, there are different teams involved in bringing out a single product. It could consist three teams, one for analog design, one for digital design and another team for system integration.
The system integration team would be responsible for using custom ICs other ‘off the shelf’ ICs to bring out the final product. Truly speaking, an ‘end to end design flow’ should include the entire process, right up to the point of shipping the complete usable product to the customer. It is thus left to the design managers to weigh the tradeoffs involved at each stage. For example, consider the aspect of using completely off the shelf chips 10 to tape out the A/D converter as opposed to using a custom ICs or, using a custom built digital chip along with an analog off shelf comparator and an 8 bit D/A to make the SAR A/D.
There are many such options that require managerial decisions. But the important points to be kept in mind while making these decisions are listed below. ?? Time span of the design. ?? Cost. ?? Meeting the specifications. One of the research goals of this thesis in design flow discussed above is to provide a streamlined path to tape out mixed signal chips that interface to standard MCU and DSP chips and their development platforms. Thus, the one of the objectives, in a broader sense, is to enable the development of programmable mixed signal systems.
The chapters in this document are sectioned according to the general design flow. Chapter 1 reviews a generic design flow, the most common methods of approach, and the intent of this document. Chapter 2 deals with the first stage of design, which is capturing an idea and the initial design entry. Chapter 3 deals with the behavioral descriptions of circuits. Chapter 4 discusses structural descriptions and chapter 5 discusses the layout process. The 6th chapter, namely, the ‘summary and conclusion’, summarizes this document and gives a broad overview of what future work can be done. 11 CHAPTER 2 DESIGN IDEA
This is probably the only stage in the design flow that does not find the necessity of a computer. This is also the first phase of design after receiving the specifications for the IC. In this stage, the design team makes decisions regarding the general build up of the chip. Experience is recommended at this stage of design. In fact, in large corporations, team managers are usually the key players at such a stage. They are the people who usually make decisions about the main functional blocks of the chip. At the end of this stage, a consensus of the block level specification of the chip is evolved.
Figure 2. 1 shows the current status of the design flow up to chapter 2. 12 Figure 2. 1: Current status, Design Idea 13 2. 1 EVOLVING A DESIGN IDEA As mentioned earlier, an example based explanation approach is used in this thesis. The example chosen is that of a successive approximation register (SAR). Assume that the design team is a university based team and the following ‘specs sheet’ (table 2. 1) was given. Specs Sheet 1. Build a SAR type digital circuit, which interfaces to an analog block. 2. Required resolution of SAR is 8 bits. 3. Conversion must start when the signal ‘Soc’ is asserted. 4.
The circuit resets itself when the signal ‘Rst’ is asserted. 5. ‘Eoc’ must be asserted when the result is valid on the output bus. 6. The clock frequency is 1Mhz. Table 2. 1: SAR specs sheet 2. 2 CAPTURING A DESIGN IDEA Interface block diagram: The first requirement is that of a ‘black box’ like block diagram, which illustrates the interface to the outside world. Figure 2. 2 illustrates that. The hypothetical chip that is to be built is called MYCHIP. 14 Inputs Outputs Figure 2. 2: Black box like block diagram Functional block diagram: A more detailed block diagram is drawn which shows the major functional blocks of the IC.
Figure 2. 3: Functional block diagram 15 Ensuring the functionality: In most cases, a flow chart is drawn to ensure that the understanding of the working of the circuit (in this case, the SAR) is correct. Figure 2. 4 shows the flow chart of the SAR Figure 2. 4: Flow chart of SAR 16 2. 3 ABSTRACT DESIGN IDEA SIMULATION The flow chart in figure 2. 4 needs to be simulated to ensure that the theory of operation is correct. The only way to test it is to program it into some sort of CAD tool. The most common answer would be a programming language.
But because of the issue of concurrency, a HDL is used for simulation instead of a programming language. Section 2. 4 describes a design idea simulation using a programming language like C. 2. 4 SIMULATION OF THEORY OF OPERATION USING C A sample of the code used for simulation is shown in table 2. 2. The results obtained are as expected (Note that depending on its construction, the probability of 1 lsb error in a SAR is 0. 5). Figures 2. 4. 1,2. 4. 2,2. 4. 3 show the simulation results. For simplicity it is assumed that the input voltage to MYCHIP ranges from 0 to 255. 17 include #include #include int d[7]; int vin=255; void main (void) { void initialize (void); void incr (int); void decr (int); int compare ( void ); int i,k; initialize(); for (i=7;i>0;i=i-1) { incr(i); k=compare(); if (k==1) decr(i); printf(“d[7:0]=%d%d%d%d%d%d%d%d
“,d[7],d[6],d[5],d[4],d[3],d[2], d[1],d[0]); } printf (”
Vin= %d
“,vin); printf(”
Finalanswer d[7:0]=%d%d%d%d%d%d%d%d
“,d[7],d[6],d[5],d[4],d[3],d[2],d[1],d[0]); } void initialize (void) { int i; for (i=0;i 0) begin d[i]=1’b1; if(d ; vin) begin d[i]=1’b0; end i=i-1; end end endmodule Table 2. 3: Verilog Code for design idea simulation 22 2. 6
INTRODUCTION TO TESTBENCHER TestBencher Pro is a design and verification tool suite marketed by SynaptiCad (www. synapticad. com). VeriLogger Pro is a part of this design suite that is capable of compiling Verilog code. VeriLogger Pro is also a complete design and verification environment for ASIC and FPGA designers. TestBencher contains a new type of Verilog simulation environment that combines all the features of a traditional Verilog simulator with an automatic graphical test vector generator. Test vectors can be imported or exported from HP logic analyzers, pattern generators, 3rd party VHDL, Verilog, and SPICE for reuse.
Simulation features include waveform viewing, optimized gate-level simulation, single-step debugging, point-and-click breakpoints, hierarchical browser for project management, and batch execution. Figure 2. 8 shows a screen shot of TestBencher interface. And figure 2. 9 shows a screen capture of the simulation result. For detailed simulation results, refer to appendix A. 23 Module under test Simulation window Verilog Editor window Figure 2. 8: TestBencher Overview 24 Input Result Figure 2. 9: d[7:0] shows the result for input voltage of 44. At the end of the design idea capture stage, the overall system block diagram is decided upon.
The next step of the design is to model each of the blocks separately. 25 CHAPTER 3 BEHAVIORAL DESCRIPTION The behavioral approach to modeling hardware components is different from circuit design in that it does not necessarily reflect how the design is implemented. It is basically an algorithmic and black box approach to modeling. It accurately models what happens on the inputs and outputs of the black box, but what is inside the box or how the box is constructed is unknown. A behavioral description is usually used in two ways. First, it can be used to model complex components that would be tedious to model using the other methods.
This might be the case for example, if you wish to simulate the operation of your custom design connected to a commercial part like a microprocessor. In this case, the microprocessor is complex and its internal operation is irrelevant (only the external behavior is important) so it would probably be modeled using the behavioral style. Second, the behavioral capabilities of HDLs can be more powerful and are more convenient for some designs, especially if an efficient tool that converts some aspects of behavioral code into RTL exists. 26 Figure 3. 1 shows the current status of the design flow up to this chapter.
Figure 3. 1: current status, behavioral description 27 3. 1 BEHAVIORAL DESCRIPTION TO RTL The designer starts with an abstract description of the circuit called the behavioral model. This kind of description is used primarily to verify the methodology and functioning of the circuit. The next step is to transform this description into something closer to electronic circuitry. In other words, the behavioral description needs to be converted to RTL (Register Transfer Language). A functional or RTL description describes a circuit in terms of its registers and the combinatorial logic between the registers.
This ‘behavioral synthesis’ can either be done manually or automatically by software. The essential goal of doing this is to use logic synthesizers that takes this form of description and synthesizes it to sets of registers and combinational logic, which can be readily shipped to FPGA and ASIC vendors. Table 3. 1 shows a Verilog behavioral description of a Dflipflop. In sec 3. 1, an illustration of converting this behavioral code to RTL using X-HDL3 is shown. module dffbehavioral (q,qbar,d,clk,rst); input d,clk,rst; output q,qbar; reg q,qbar; always @ (posedge clk) begin q=d; qbar=~d; Table 3. 1: Behavioral description of a Dflipflop 28 continued) Table 3. 1: (continued) if (rst == 1’b1) begin q=1’b0; qbar=1’b1; end end endmodule 3. 2 INTRODUCTION TO X-HDL3 X-hdl3 is a useful tool in converting behavioral code to RTL. Given in table 3. 2 is an RTL description of the sample file in table 3. 1. Figure 3. 2 shows the option in XHDL, which is used to make the code synthesizable (RTL). 29 Synopsis synthesizable Figure 3. 2: X-HDL3 Interface for Behavioral to RTL. 30 //——————————————————————————————-// Wed May 16 02:08:44 2001 // Input file : C:/Program Files/xhdl3/bin/dffbehavioral. // Design name : dffbehavioral // Author : // Company : // Description : //——————————————————————————————-// module dffbehavioral (q, qbar, d, clk, rst); output q; wire q; output qbar; wire qbar; input d; input clk; input rst; reg q_xhdl1; reg qbar_xhdl2; assign q = q_xhdl1 ; assign qbar = qbar_xhdl2 ; always @(posedge clk) begin : xhdl_0 reg q_xhdl1_xhdl3; reg qbar_xhdl2_xhdl4; q_xhdl1_xhdl3 = d; qbar_xhdl2_xhdl4 = ~d; if (rst) begin q_xhdl1_xhdl3 = 1’b0; qbar_xhdl2_xhdl4 = 1’b1; end q_xhdl1
