Radix-4 Booth Multiplier Essay



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DEDICATION: This project report is dedicated to our parents, our revered teachers & all our dearest friends. | KOUSTUV INSTITUTE OF SELF DOMAIN (Affiliated to BPUT University)Bhubaneswar -751024, Orissa, India. | | DEPARTMENT OF ELECTRONICS & TELECOMMUNICATION ENGINEERING CERTIFICATE This is to certify that the project work titled “DESIGN AND IMPLEMENTATION OF RADIX-4 BOOTH MULTIPLIER USING VHDL” is a bonafide work of TANIMA PADHEESRUJITA PADMINI DASM.

SAILAJAPUSPITA KUMARI PARIDA | 0501208124060120801206012081810601208044| carried out in partial fulfillment of the requirements for awarding the degree of Bachelor of Technology in Electronics and Telecommunication Engineering discipline in KOUSTUV INSTITUTE OF SELF DOMAIN under Biju Pattanaik University of Technology ( BPUT) during the academic year 2009-2010. Miss. PANCHAMI PADMASANA,Mr. TARUN SETHI Lecturers Project Guide| Prof.

SUBRAT MOHANTY Principal KISD| | KOUSTUV INSTITUTE OF SELF DOMAIN (Affiliated to BPUT University)Bhubaneswar -751024, Orissa, India. | | DEPARTMENT OF ELECTRONICS & TELECOMMUNICATION ENGINEERING ACKNOWLEDGEMENT: We remain obliged to our institute KOUSTUV INSTITUTE OF SELF DOMAIN, Bhubaneswar for giving us such an opportunity to present this project report in partial fulfillment for the award of B-Tech in Electronics and Telecommunication Engineering. We owe our special depth of gratitude to Miss. Panchami Padmasana & Mr.

Tarun Sethi for his kind permission and persistent encouragement without which this piece of work wouldn’t come to limelight. Our sincere gratitude and indebtedness goes to all the teachers for their academic suggestion in pioneering this presentation. Lastly, we are thankful to our friends for their guidance and help. CONTENTS Abstract……………………………………………………… 05 List of Figures……………………………………………… ii List of Tables………………………………………………… ……. iii Introduction…………. …………………………………………. 9 VHDL …………………………………………………………… 14 Filters……………………… ……………………………………26 Type of filters………………………………………………….. 9 Adders…. ………………………….. …………………………. 31 Binary multipliers….. ……………. ……………………. …….. 41 Results……………………………………………………………………………. 54 Conclusion………………………………………………………57 References……………………………………………………. ABSTRACT: Low power consumption and smaller area are some of the most important criteria for the fabrication of DSP systems and high performance systems. Optimizing the speed and area of the multiplier is a major design issue. However, area and speed are usually conflicting constraints so that improving speed results mostly in larger areas.

In our project we try to determine the best solution to this problem by comparing a few multipliers. This project presents an efficient implementation of high speed multiplier using the shift and add method, Radix_4 modified Booth multiplier algorithm. The parallel multipliers like radix 4 modified booth multiplier do the computations using lesser adders and lesser iterative steps. As a result of which they occupy lesser space as compared to the serial multiplier. This is a very important criterion because in the fabrication of chips and high performance system requires components which are as small as possible.

In our project when we compare the power consumption of all the multipliers we find that serial multipliers consume more power. So where power is an important criterion there we should prefer parallel multipliers like booth multipliers to serial multipliers. The low power consumption quality of booth multiplier makes it a preferred choice in designing different circuits. In this project we first designed three different types of multipliers using shift and method, radix 4 modified booth multiplier algorithm. We used different type of adders like sixteen bit full adder in designing those multipliers.

The result of our project helps us to choose a better option between serial and parallel multiplier in fabricating different systems. Multipliers form one of the most important components of many systems. So by analyzing the working of different multipliers helps to frame a better system with less power consumption and lesser area. CHAPTER 1 INTRODUCTION LOW POWER CONSUMPTION INTRODUCTION Multipliers are key components of many high performance systems such as FIR filters, microprocessors, digital signal processors, etc.

A system’s performance is generally determined by the performance of the multiplier because the multiplier is generally the slowest clement in the system. Furthermore, it is generally the most area consuming. Hence, optimizing the speed and area of the multiplier is a major design issue. However, area and speed are usually conflicting constraints so that improving speed results mostly in larger areas. As a result, whole spectrums of multipliers with different area-speed constraints have been designed with fully parallel multipliers at one end of the spectrum and fully serial multipliers at the other end.

In between are digit serial multipliers where single digits consisting of several bits are operated on. These multipliers have moderate performance in both speed and area. However, existing digit serial multipliers have been plagued by complicated switching systems and/or irregularities in design. Radix 2^n multipliers which operate on digits in a parallel fashion instead of bits bring the pipelining to the digit level and avoid most of the above problems. They were introduced by M. K. Ibrahim in 1993. These structures are iterative and modular.

The pipelining done at the digit level brings the benefit of constant operation speed irrespective of the size of the multiplier. The clock speed is only determined by the digit size which is already fixed before the design is implemented. CHAPTER 2 ADDERS HALF ADDER FULL ADDER ADDER In electronics, an adder is a digital circuit that performs addition of numbers. In modern computers adders reside in the arithmetic logic unit (ALU) where other operations are performed. Although adders can be constructed for many numerical representations, such as Binary-coded decimal or excess-3, the most common adders operate on binary numbers.

In cases where two’s complement is being used to represent negative numbers it is trivial to modify an adder into an adder-subtracter Types of adders For single bit adders, there are two general types. A half adder has two inputs, generally labeled A and B, and two outputs, the sum S and carry C. S is the two-bit XOR of A and B, and C is the AND of A and B. Essentially the output of a half adder is the sum of two one-bit numbers, with C being the most significant of these two outputs. The second type of single bit adder is the full adder.

The full adder takes into account a carry input such that multiple adders can be used to add larger numbers. To remove ambiguity between the input and output carry lines, the carry in is labeled Ci or Cin while the carry out is labeled Co or Cout. Half adder Half adder circuit diagram A half adder is a logical circuit that performs an addition operation on two binary digits. The half adder produces a sum and a carry value which are both binary digits. C = A . B Following is the logic table for a half adder: Input Output A B C S 0 0 0 0 0 1 0 1 0 0 1 1 1 1 0 Full adder Inputs: {A, B, Carry In} _ Outputs: {Sum, Carry Out} Schematic symbol for a 1-bit full adder A full adder is a logical circuit that performs an addition operation on three binary digits. The full adder produces a sum and carries value, which are both binary digits. It can be combined with other full adders (see below) or work on its own. Input Output A B Ci Co S 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 1 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1

Note that the final OR gate before the carry-out output may be replaced by an XOR gate without altering the resulting logic. This is because the only discrepancy between OR and XOR gates occurs when both inputs are 1; for the adder shown here, one can check this is never possible. Using only two types of gates is convenient if one desires to implement the adder directly using common IC chips. A full adder can be constructed from two half adders by connecting A and B to the input of one half adder, connecting the sum from that to an input to the second adder, connecting Ci to the other input and or the two carry outputs.

Equivalently, S could be made the three-bit xor of A, B, and Ci and Co could be made the three-bit majority function of A, B, and Ci. The output of the full adder is the two-bit arithmetic sum of three one-bit numbers. CHAPTER 3 BINARY MULTIPLIER SERIAL AND PARALLEL MULTIPLIERS A Binary multiplier is an electronic hardware device used in digital electronics or a computer or other electronic device to perform rapid multiplication of two numbers in binary representation. It is built using binary adders. The rules for binary multiplication can be stated as follows If the multiplier digit is a 1, the multiplicand is simply copied down and represents the product. * If the multiplier digit is a 0 the product is also 0. For designing a multiplier circuit we should have circuitry to provide or do the following three things: * It should be capable identifying whether a bit is 0 or 1. * It should be capable of shifting left partial products. * It should be able to add all the partial products to give the products as sum of partial products. * It should examine the sign bits. If they are alike, the sign of the product will be a positive, if the sign bits are opposite product will be negative.

The sign bit of the product stored with above criteria should be displayed along with the product. From the above discussion we observe that it is not necessary to wait until all the partial products have been formed before summing them. In fact the addition of partial product can be carried out as soon as the partial product is formed. Notations: ? a – multiplicand ? b – multiplier ? p – product Binary multiplication (eg n=4) p=a? b an? 1 an? 2_a1a0 bn? 1bn? 2_b1b0 p2 n? 1 p2 n? 2_p1 p0 x x x x a x x x x b ——— x x x x b0a20 x x x x b1a21 x x x x b2a22 x x x x b3a23 ————— x x x x x x x p MULTIPLY ACCUMULATE CIRCUITS Multiplication followed by accumulation is a operation in many digital systems, particularly those highly interconnected like digital, filters, neural networks, data quantizers, etc. One typical MAC (multiply-accumulate) architecture is illustrated in figure. It consists of multiplying 2 values, then adding the result to the previously accumulated value, which must then be restored in the registers for future accumulations. Another feature of MAC circuit is that it must check for overflow, which might happen when the number of MAC operation is large.

This design can be done using component because we have already design each of the units shown in figure. However since it is relatively simple circuit, it can also be designed directly. In any case the MAC circuit, as a whole, can be used as a component in application like digital filters and neural networks. ARCHITECTURE OF A RADIX 2^n MULTIPLIER The architecture of a radix 2^n multiplier is given in the Figure. The above block diagram shows the multiplication of two numbers with four digits each. These numbers are denoted as V and U while the digit size was chosen as four bits.

The reason for this will become apparent in the following sections. Each circle in the figure corresponds to a radix cell which is the heart of the design. Every radix cell has four digit inputs and two digit outputs. The input digits are also fed through the corresponding cells. The dots in the figure represent latches for pipelining. Every dot consists of four latches. The ellipses represent adders which are included to calculate the higher order bits. They do not fit the regularity of the design as they are used to “terminate” the design at the boundary.

The outputs are again in terms of four bit digits and are shown by W’s. The 1’s denote the clock period at which the data appear. BOOTH MULTIPLIER The decision to use a Radix-4 modified Booth algorithm rather than Radix-2 Booth algorithm is that in Radix-4, the number of partial products is reduced to n/2. Though Wallace Tree structure multipliers could be used but in this format, the multiplier array becomes very large and requires large numbers of logic gates and interconnecting wires which makes the chip design large and slows down the operating speed.

Booth Multiplication Algorithm Booth Multiplication Algorithm for radix 2 Booth algorithm gives a procedure for multiplying binary integers in signed –2’s complement representation. I will illustrate the booth algorithm with the following example: Example, 2ten x (-4)ten 0010two * 1100two Step 1: Making the Booth table I. From the two numbers, pick the number with the smallest difference between a series of consecutive numbers, and make it a multiplier. i. e. , 0010 — From 0 to 0 no change, 0 to 1 one change, 1 to 0 another change, and so there are two changes on this one 100 — From 1 to 1 no change, 1 to 0 one change, 0 to 0 no change, so there is only one change on this one. Therefore, multiplication of 2 x (– 4), where 2ten (0010two) is the multiplicand and (-4)ten (1100two) is the multiplier. II. Let X = 1100 (multiplier) Let Y = 0010 (multiplicand) Take the 2’s complement of Y and call it –Y –Y = 1110 III. Load the X value in the table. IV. Load 0 for X-1 value it should be the previous first least significant bit of X V. Load 0 in U and V rows which will have the product of X and Y at the end of operation. VI.

Make four rows for each cycle; this is because we are multiplying four bits numbers. Step 2: Booth Algorithm Booth algorithm requires examination of the multiplier bits, and shifting of the partial product. Prior to the shifting, the multiplicand may be added to partial product, subtracted from the partial product, or left unchanged according to the following rules: Look at the first least significant bits of the multiplier “X”, and the previous least significant bits of the multiplier “X – 1”. I. 0 0 Shift only 1 1 Shift only. 0 1 Add Y to U, and shift 1 0 Subtract Y from U, and shift or add (-Y) to U and shift II.

Take U ; V together and shift arithmetic right shift which preserves the sign bit of 2’s complement number. Thus a positive number remains positive, and a negative number remains negative. III. Shift X circular right shift because this will prevent us from using two registers for the X value. Booth multiplication algorithm for radix 4 One of the solutions of realizing high speed multipliers is to enhance parallelism which helps to decrease the number of subsequent calculation stages. The original version of the Booth algorithm (Radix-2) had two drawbacks.

They are: * The number of add subtract operations and the number of shift operations becomes variable and becomes inconvenient in designing parallel multipliers. * The algorithm becomes inefficient when there are isolated 1’s. These problems are overcome by using modified Radix4 Booth algorithm which scan strings of three bits with the algorithm given below: 1) Extend the sign bit 1 position if necessary to ensure that n is even. 2) Append a 0 to the right of the LSB of the multiplier. 3) According to the value of each vector, each Partial Product will be 0, +y, -y, +2y or -2y.

The negative values of y are made by taking the 2’s complement and in this paper Carry-look-ahead (CLA) fast adders are used. The multiplication of y is done by shifting y by one bit to the left. Thus, in any case, in designing n-bit parallel multipliers, only n/2 partial products are generated. CHAPTER 4 VHDL :THE LANGUAGE EXPERIMENTAL Many DSP applications demand high throughput and real-time response, performance constraints that often dictate unique architectures with high levels of concurrency. DSP designers need the capability to manipulate and evaluate complex algorithms to extract the necessary level of concurrency.

Performance constraints can also be addressed by applying alternative technologies. A change at the implementation level of design by the insertion of a new technology can often make viable an existing marginal algorithm or architecture. The VHDL language supports these modeling needs at the algorithm or behavioral level, and at the implementation or structural level. It provides a versatile set of description facilities to model DSP circuits from the system level to the gate level. Recently, we have also noticed efforts to include circuit-level modeling in VHDL.

At the system level we can build behavioral models to describe algorithms and architectures. We would use concurrent processes with constructs common to many high-level languages, such as if, case, loop, wait, and assert statements. VHDL also includes user-defined types, functions, procedures, and packages. ” In many respects VHDL is a very powerful, high-level, concurrent programming language. At the implementation level we can build structural models using component instantiation statements that connect and invoke subcomponents. The VHDL generate statement provides ease of block replication and control.

A dataflow level of description offers a combination of the behavioral and structural levels of description. VHDL lets us use all three levels to describe a single component. Most importantly, the standardization of VHDL has spurred the development of model libraries and design and development tools at every level of abstraction. VHDL, as a consensus description language and design environment, offers design tool portability, easy technical exchange, and technology insertion. VHDL: The language An entity declaration, or entity, combined with architecture or body constitutes a VHDL model.

VHDL calls the entity-architecture pair a design entity. By describing alternative architectures for an entity, we can configure a VHDL model for a specific level of investigation. The entity contains the interface description common to the alternative architectures. It communicates with other entities and the environment through ports and generics. Generic information particularizes an entity by specifying environment constants such as register size or delay value. For example, entity A is port (x, y: in real; z: out real); generic (delay: time); end A;

The architecture contains declarative and statement sections. Declarations form the region before the reserved word begin and can declare local elements such as signals and components. Statements appear after begin and can contain concurrent statements. For instance, architecture B of A is component M port ( j : in real ; k : out real); end component; signal a,b,c real := 0. 0; begin “concurrent statements” end B; The variety of concurrent statement types gives VHDL the descriptive power to create and combine models at the structural, dataflow, and behavioral levels into one simulation model.

The structural type of description makes use of component instantiation statements to invoke models described elsewhere. After declaring components, we use them in the component instantiation statement, assigning ports to local signals or other ports and giving values to generics. invert: M port map ( j => a ; k => c); We can then bind the components to other design entities through configuration specifications in VHDL’s architecture declarative section or through separate configuration declarations.

The dataflow style makes wide use of a number of types of concurrent signal assignment statements, which associate a target signal with an expression and a delay. The list of signals appearing in the expression is the sensitivity list; the expression must be evaluated for any change on any of these signals. The target signals obtain new values after the delay specified in the signal assignment statement. If no delay is specified, the signal assignment occurs during the next simulation cycle: c <= a + b after delay; VHDL also includes conditional and selected signal assignment statements.

It uses block statements to group signal assignment statements and makes them synchronous with a guarded condition. Block statements can also contain ports and generics to provide more modularity in the descriptions. We commonly use concurrent process statements when we wish to describe hardware at the behavioral level of abstraction. The process statement consists of declarations and procedural types of statements that make up the sequential program. Wait and assert statements add to the descriptive power of the process statements for modeling concurrent actions: process begin ariable i : real := 1. 0; wait on a; i = b * 3. 0; c <= i after delay; end process; Other concurrent statements include the concurrent assertion statement, concurrent procedure call, and generate statement. Packages are design units that permit types and objects to be shared. Arithmetic operations dominate the execution time of most Digital Signal Processing (DSP) algorithms and currently the time it takes to execute a multiplication operation is still the dominating factor in determining the instruction cycle time of a DSP chip and Reduced Instruction Set Computers (RISC).

Among the many methods of implementing high speed parallel multipliers, there is one basic approach namely Booth algorithm. Power consumption in VLSI DSPs has gained special attention due to the proliferation of high-performance portable battery-powered electronic devices such as cellular phones, laptop computers, etc. DSP applications require high computational speed and, at the same time, suffer from stringent power dissipation constraints. Multiplier modules are common to many DSP applications. The fastest types of multipliers are parallel multipliers. Among these, the Wallace multiplier is among the fastest.

However, they suffer from a bad regularity. Hence, when regularity, high performance and low power are primary concerns, Booth multipliers tend to be the primary choice. Booth multipliers allow the operation on signed operands in 2’s-complement. They derive from array multipliers where, for each bit in a partial product line, an encoding scheme is used to determine if this bit is positive, negative or zero. The Modified Booth algorithm achieves a major performance improvement through radix-4 encoding. In this algorithm each partial product line operates on 2 bits at a time, thereby reducing the total number of the partial products.

This is particularly true for operands using 16 bits or more. CHAPTER 5 ANALYSIS VHDL CODES FOR MULTIPLIER ANALYSIS VHDL code for sixteen bit adder ———————————————————————————- library IEEE; use IEEE. STD_LOGIC_1164. ALL; use IEEE. STD_LOGIC_ARITH. ALL; use IEEE. STD_LOGIC_SIGNED. ALL; —- Uncomment the following library declaration if instantiating —- any Xilinx primitives in this code. –library UNISIM; –use UNISIM. VComponents. all; entity sixteenbit_fa is Port ( a : in STD_LOGIC_VECTOR (15 downto 0); b : in STD_LOGIC_VECTOR (15 downto 0); – cin : in STD_LOGIC; yout : out STD_LOGIC_VECTOR (15 downto 0); cout : out STD_LOGIC); end sixteenbit_fa; architecture Behavioral of sixteenbit_fa is signal s: std_logic_vector(15 downto 0); signal carry1: std_logic_vector(16 downto 0); COMPONENT twobit_add PORT( a : IN std_logic; b : IN std_logic; cin : IN std_logic; sum : OUT std_logic; cout : OUT std_logic ); END COMPONENT; begin carry1(0)<=’0′; g1 : for i in 0 to 15 generate f0 : twobit_add PORT MAP(a(i), b(i),carry1(i),yout(i), carry1(i+1)); — inter_carr<=carry(i+1); end generate g1; cout<=carry1(16); nd Behavioral; VHDL code for array multiplier library IEEE; use IEEE. STD_LOGIC_1164. ALL; use IEEE. STD_LOGIC_ARITH. ALL; use IEEE. STD_LOGIC_UNSIGNED. ALL; —- Uncomment the following library declaration if instantiating —- any Xilinx primitives in this code. –library UNISIM; –use UNISIM. VComponents. all; entity mult64 is Port ( clk:in std_logic; –rst:in std_logic; a : in std_logic_vector(7 downto 0); b : in std_logic_vector(7 downto 0); prod : out std_logic_vector(15 downto 0)); end mult64; rchitecture Behavioral of mult64 is constant n:integer :=8; subtype plary is std_logic_vector(n-1 downto 0); type pary is array(0 to n) of plary; signal pp,pc,ps:pary; begin pgen:for j in 0 to n-1 generate pgen1:for k in 0 to n-1 generate pp(j)(k)<=a(k) and b(j); end generate; pc(0)(j)<=’0′; end generate; ps(0)<=pp(0); prod(0)<=pp(0)(0); addr:for j in 1 to n-1 generate addc:for k in 0 to n-2 generate ps(j)(k)<=pp(j)(k) xor pc(j-1)(k) xor ps(j-1)(k+1); pc(j)(k)<=(pp(j)(k) and pc(j-1)(k)) or (pp(j)(k) and ps(j-1)(k+1)) or (pc(j-1)(k)and ps(j-1)(k+1)); end generate; prod(j)<=ps(j)(0); s(j)(n-1)<=pp(j)(n-1); end generate; pc(n)(0)<=’0′; addlast:for k in 1 to n-1 generate ps(n)(k)<=pc(n)(k-1) xor pc(n-1)(k-1) xor ps(n-1)(k); pc(n)(k)<=(pc(n)(k-1) and pc(n-1)(k-1)) or (pc(n)(k-1) and ps(n-1)(k)) or (pc(n-1)(k-1)and ps(n-1)(k)); end generate; prod(2*n-1)<=pc(n)(n-1); prod(2*n-2 downto n)<=ps(n)(n-1 downto 1); end Behavioral; VHDL code for booth encoder ———————————————————————————- library IEEE; use IEEE. STD_LOGIC_1164. ALL; use IEEE. STD_LOGIC_ARITH. ALL; use IEEE. STD_LOGIC_SIGNED. ALL; use ieee. std_logic_arith. ll; —- Uncomment the following library declaration if instantiating —- any Xilinx primitives in this code. –library UNISIM; –use UNISIM. VComponents. all; entity booth_mult is Port ( a : in STD_LOGIC_VECTOR (7 downto 0); b : in STD_LOGIC_VECTOR (7 downto 0); yout : out STD_LOGIC_VECTOR (15 downto 0); ovf: out std_logic); end booth_mult; architecture Behavioral of booth_mult is COMPONENT booth_encoder PORT( a : IN std_logic_vector(7 downto 0); arg : IN std_logic_vector(2 downto 0); pprod : OUT std_logic_vector(15 downto 0) );

END COMPONENT; COMPONENT sixteenbit_fa PORT( a : IN std_logic_vector(15 downto 0); b : IN std_logic_vector(15 downto 0); yout : OUT std_logic_vector(15 downto 0); cout : OUT std_logic ); END COMPONENT; signal pp1,pp2,pp3,pp4,s1,s2,s3, sum1,sum2,sum3: std_logic_vector(15 downto 0); signal st: std_logic_vector(2 downto 0); signal k1,k2,k3: std_logic; begin st<=b(1 downto 0)&’0′; u0: booth_encoder PORT MAP(a,st,pp1); u1: booth_encoder PORT MAP(a,b(3 downto 1),pp2); u2: booth_encoder PORT MAP(a,b(5 downto 3),pp3); u3: booth_encoder PORT MAP(a,b(7 downto 5),pp4); s1<=pp2(13 downto 0)&”00″; 2<=pp3(11 downto 0)&”0000″; s3<=pp4(9 downto 0)&”000000″; u4: sixteenbit_fa PORT MAP(pp1,s1,sum1,k1); u5: sixteenbit_fa PORT MAP(sum1,s2,sum2,k2); u6: sixteenbit_fa PORT MAP(sum2,s3,yout,ovf); end Behavioral; VHDL code for booth multiplier radix 4 ——————————————————————————– library IEEE; use IEEE. STD_LOGIC_1164. ALL; use IEEE. STD_LOGIC_ARITH. ALL; use IEEE. STD_LOGIC_SIGNED. ALL; use ieee. numeric_std. all; —- Uncomment the following library declaration if instantiating —- any Xilinx primitives in this code. –library UNISIM; -use UNISIM. VComponents. all; entity booth_encoder is — generic(N : integer:=8); Port ( a : in std_logic_vector(7 downto 0); arg : in std_logic_vector(2 downto 0); pprod : out std_logic_vector(15 downto 0)); end booth_encoder; architecture Behavioral of booth_encoder is function encoder(arg1: std_logic_vector(2 downto 0); data:std_logic_vector(7downto 0)) return std_logic_vector is variable temp,temp1,temp2: std_logic_vector(8 downto 0); variable sign: std_logic; begin case arg1 is when “001”|”010″ => if data <0 then temp:=’1’& data; else emp:=’0’&data; end if; when “011” => if data<0 then temp1:=’1’&data; temp:=temp1(7 downto 0)&’0′; else temp:=’0’&data(6 downto 0)&’0′; end if ; when “100” => if data<0 then temp1:=’1’&data; temp2:=(not temp1)+”000000001″; temp:=(temp2(7 downto 0)&’0′); else emp1:=’0’&data; temp2:=(not temp1)+”000000001″; temp:=(temp2(7 downto 0)&’0′); end if; when “101”|”110″ => if data < 0 then temp1:=’1’&data; temp:=not(temp1)+”000000001″; else temp1:=’0’&data; temp:=(not temp1)+”000000001″; end if; hen others => temp:=”000000000″; –“(others=;’0′); end case; return temp; end encoder; signal s1: std_logic_vector(8 downto 0); signal s2: std_logic; begin s1;=encoder(arg,a); –s2<=s1(8); –pprod<=s2&s2&s2&s2&s2&s2&s2&s2&s1(7 downto 0); pprod<=sxt(s1,16); end Behavioral; CHAPTER 6 RESULTS RESULTS OF DIFFERENT MULTIPLIERS ARRAY MULTIPLIER Number of Slices| 229| Number of 4 input LUTs| 302| Number of bonded INPUT| 16|

Number of bonded OUTPUT| 16| CLB Logic Power| 104mW| RADIX 2 BOOTH MULTIPLIER Number of Slices| 130| Number of 4 input LUTs| 249| Number of bonded INPUT| 16| Number of bonded OUTPUT| 17| CLB Logic Power| 79mW| RADIX 4 BOOTH MULTIPLIER Number of Slices| 229| Number of 4 input LUTs| 302| Number of bonded INPUT| 16| Number of bonded OUTPUT| 16| CLB Logic Power| 47mW| MULTIPLIER OUTPUT CHAPTER 8 CONCLUSION CONCLUSION

Our project gives a clear concept of different multiplier. We found that the parallel multipliers are much option than the serial multiplier. We concluded this from the result of power consumption and the total area. In case of parallel multipliers, the total area is much less than that of serial multipliers. Hence the power consumption is also less. This is clearly depicted in our results. This speeds up the calculation and makes the system faster. While comparing the radix 2 and the radix 4 booth multipliers we found that radix 4 consumes lesser power than that of radix 2.

This is because it uses almost half number of iteration and adders when compared to radix 2. When all the three multipliers were compared we found that array multipliers are most power consuming and have the maximum area. This is because it uses a large number of adders. As a result it slows down the system because now the system has to do a lot of calculation. Multipliers are one the most important component of many systems. So we always need to find a better solution in case of multipliers. Our multipliers should always consume less power and cover less power.

So through our project we try to determine which of the three algorithms works the best. In the end we determine that radix 4 modified booth algorithm works the best. REFERENCES Websites referred: 1. www. wikipedia. com 2. www. howstuffswork. com 3. www. xilinx. com Books referred: 1. Circuit Design using VHDL, by Pedroni , page number 285-293. 2. VHDL by Sjoholm Stefan 3. VHDL by B Bhaskar 4. Digital Signal Processing by Johny R Johnson ,PHI publications. 5. Digital Signal Processing by Vallavraj ; Salivhanan, TMH publications


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